Principal Hardware Development Engineer

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We are seeking a highly experienced Principal Engineer for Co-Packaged Optics (CPO) and Near-Packaged Optics (NPO) to lead the architecture, design, implementation, integration, and validation of next-generation optical interconnect solutions for AI scale-up and scale-out platforms.

This role will provide end-to-end technical leadership across optical engines, high-speed electrical interfaces, ASIC integration, package and board design, signal integrity, power integrity, thermal and mechanical design, firmware, diagnostics, and system-level validation. The successful candidate will translate platform requirements into robust CPO and NPO architectures and drive those architectures from early concept and specification development through design implementation, platform bring-up, qualification, and production readiness.

The ideal candidate will bring deep expertise in CPO and NPO system architecture, silicon photonics, optical-engine integration, 100G and 200G per-lane PAM4 interfaces, 400G, 800G, and 1.6T optical technologies, high-speed SerDes, channel design, FEC, link performance, and system-level debug.

You will collaborate closely with architecture, ASIC, package, board, signal integrity, power integrity, thermal, mechanical, firmware, diagnostics, platform engineering, manufacturing, reliability, and external technology partners. You will establish technical requirements, resolve complex cross-domain issues, and influence AMD’s long-term optical interconnect architecture and technology roadmap.

• Lead the architecture, design, implementation, integration, and validation of CPO and NPO solutions for next-generation AI scale-up and scale-out platforms.
• Define end-to-end system requirements for CPO and NPO implementations, including optical, electrical, mechanical, thermal, power, firmware, reliability, serviceability, and manufacturing requirements.
• Own the technical development of CPO and NPO solutions from early feasibility studies and architecture definition through detailed design, prototype bring-up, qualification, and production readiness.
• Develop and maintain CPO and NPO interface specifications, including optical-engine interfaces, high-speed electrical interfaces, management interfaces, control sequencing, reference clocks, reset behavior, fault handling, telemetry, and diagnostics.
• Lead the integration of optical engines, electrical integrated circuits, ASICs, packages, substrates, sockets, host boards, interposers, connectors, fibers, external laser sources, cooling solutions, and mechanical retention structures.
• Define and optimize 100G and 200G per-lane PAM4 electrical and optical link architectures supporting 400G, 800G, 1.6T, and future interconnect solutions.
• Establish electrical channel budgets and performance requirements for package, socket, connector, board, cable, and optical-engine interfaces.
• Drive SerDes and link optimization, including TX and RX equalization, link training, eye analysis, jitter analysis, BER characterization, FEC performance, latency, margining, and long-term link stability.
• Define optical link budgets and performance requirements, including transmitter power, extinction ratio, optical modulation amplitude, receiver sensitivity, stressed receiver performance, return loss, reflectance, insertion loss, crosstalk, and fiber connectivity.
• Evaluate architectural tradeoffs among CPO, NPO, onboard optics, pluggable optics, linear pluggable optics, retimed optics, co-packaged copper, and other emerging interconnect technologies.
• Lead system-level feasibility and tradeoff studies covering bandwidth density, reach, latency, power efficiency, thermal performance, reliability, manufacturability, serviceability, cost, and time to market.
• Partner with ASIC and SerDes teams to define electrical interface requirements, channel assumptions, equalization capabilities, link-training behavior, FEC architecture, clocking strategy, and diagnostic features.
• Collaborate with package, board, SI, and PI teams to optimize high-speed channel performance, power delivery, reference-clock quality, crosstalk, jitter tolerance, and overall link margin.
• Work with thermal and mechanical engineering teams to define cooling, heat-spreading, fiber-routing, connectorization, mechanical-tolerance, assembly, and serviceability requirements.
• Define external laser source architectures and requirements, including optical power delivery, laser safety, redundancy, control, monitoring, connectorization, fiber management, and fault handling.
• Develop comprehensive design verification and validation plans for component, subsystem, and full-platform testing.
• Drive electrical and optical characterization using advanced laboratory equipment, including DCA-X systems, BERTs, real-time oscilloscopes, optical spectrum analyzers, optical power meters, VNA and TDR systems, and compliance test platforms.
• Define validation methodologies for BER, FEC performance, eye margin, jitter, channel margin, link stability, traffic stress, thermal corners, voltage corners, process variation, fault recovery, and long-duration operation.
• Lead interoperability, compliance, and ecosystem validation activities with optical-engine suppliers, silicon photonics providers, connector and fiber vendors, laser suppliers, manufacturing partners, and system customers.
• Ensure alignment with applicable IEEE, OIF, CMIS, MSA, and industry standards while identifying areas where CPO and NPO implementations require platform-specific requirements or extensions.
• Develop reference architectures, design guidelines, interface-control documents, validation specifications, compliance methodologies, and integration best practices.
• Drive implementation readiness through architecture reviews, design reviews, schematic and layout reviews, SI and PI reviews, thermal reviews, FMEA activities, validation reviews, and production-readiness assessments.
• Identify critical technical risks and develop mitigation plans related to link margin, thermal performance, power delivery, optical coupling, fiber attach, external laser operation, component variation, aging, reliability, manufacturing yield, and field serviceability.
• Partner with manufacturing, quality, and reliability teams to define qualification requirements, test coverage, screening strategies, failure-analysis processes, and production monitoring.
• Develop Python-based automation for test execution, equipment control, data collection, statistical analysis, characterization, visualization, and reporting.
• Drive issue resolution and technical closure with external suppliers and ecosystem partners, including clear ownership, root-cause analysis, corrective actions, and validation of implemented fixes.

PREFERRED QUALIFICATIONS

• Extensive experience in optical networking, silicon photonics, high-speed hardware design, SerDes architecture, optical-system integration, package or board design, or system-level interconnect development.
• Significant experience leading complex hardware technologies from architecture and specification through implementation, validation, qualification, and production deployment.
• Deep understanding of CPO, NPO, onboard optics, optical-engine architectures, silicon photonics, external laser sources, and high-density fiber connectivity.
• Hands-on experience with 100G and 200G per-lane PAM4 electrical and optical interfaces.

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