Senior Layout Design Engineer

Layout Design, Sr Engineer We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years translating analog circuit schematics into physical layouts that actually perform, not just pass DRC. You know that a GPIO layout is not just about routing metal, it is about understanding how a 2pF mismatch or a 10-micron shift can break ESD performance or skew I/O timing in ways the schematic never predicted. You think in cross-sections and current density maps, and you have learned to spot a latchup risk or a substrate coupling problem before it ever hits silicon.

You are comfortable sitting with a circuit designer who hands you a half-finished schematic and a set of constraints, and you know which questions to ask to turn that into a layout that meets area, performance, and reliability targets. Matching does not scare you, it is something you have done enough times to have opinions about dummy placement and orientation strategies. You have debugged parasitic extraction results at 2 a.m. and lived to tell the story.

Automation is not a nice-to-have for you, it is how you stay sane. You write scripts to check spacing rules, generate array structures, or pull reports because doing it manually fifteen times is not an option. At Synopsys, you will work on IO and analog IP that ships in real products, with a team that knows the difference between a layout that works and one that just closes.

What You'll Be Doing

• Design and own full custom analog layouts for GPIO, specialty IO, and general-purpose analog IP blocks including I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, and JTAG interfaces
• Develop high-performance LVDS layouts and crystal oscillator circuits with attention to signal integrity, noise coupling, and parasitic management
• Collaborate with circuit designers to translate schematics into physical implementations that meet area, performance, matching, and reliability specifications
• Perform layout verification including DRC, LVS, and parasitic extraction analysis, iterating with design teams to close on performance targets
• Build and maintain layout automation scripts to improve design efficiency, consistency, and quality across IP families
• Provide technical guidance and layout reviews for junior engineers, helping them develop skills in analog matching, IO frame design, and technology-specific layout techniques
• Work across global teams in the US, Europe, and Asia to align on design standards, schedules, and deliverables for multi-site IP development programs

The Impact You Will Have

• Your layouts will directly enable GPIO and specialty IO performance in Synopsys IP that powers AI, automotive, and high-performance computing chips used by leading semiconductor companies
• You will help reduce design cycle time and improve first-pass silicon success rates through high-quality layout and proactive parasitic management
• The automation scripts and layout methodologies you develop will become reusable assets across multiple IP families and process nodes
• Your technical reviews and mentorship will raise the skill level of the layout team and reduce costly respins caused by layout-induced performance issues
• You will contribute to IP roadmaps by identifying layout-driven design constraints early, influencing architecture decisions before they become problems
• The IO and analog blocks you design will ship in millions of devices, affecting real-world product performance and time to market for Synopsys customers
• You will help establish layout best practices and design guidelines that scale across a global engineering organization

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, VLSI Design, or equivalent practical experience
• 3 to 6 years of hands-on experience in analog or mixed-signal custom IC layout design
• Strong understanding of CMOS layout fundamentals including device matching, parasitic effects, electromigration, latchup, and ESD protection strategies
• Proficiency with industry-standard layout tools such as Cadence Virtuoso, Calibre, or equivalent verification and extraction platforms
• Working knowledge of scripting languages such as Python, Perl, TCL, or SKILL for layout automation and design checks
• Experience with IO frame design, pad ring assembly, or specialty interface IP layout is a strong plus
• Familiarity with parasitic extraction tools and the ability to interpret and act on R/C extraction results to meet circuit performance targets

Who You Are

• You can sit in a layout review, spot a symmetry issue or a metal density violation in seconds, and explain the fix without needing to pull up the full design
• You do not wait for perfect specs, you work with what circuit designers give you, ask clarifying questions about critical matching pairs or bias routing, and move forward
• You treat layout as a craft, not a checklist, and you care about the difference between a layout that barely passes LVS and one that is actually manufacturable and reliable
• You are comfortable working across time zones with teams in different geographies, coordinating handoffs and reviews without losing momentum
• You are the person junior engineers come to when they are stuck on a tricky matching problem or cannot figure out why their extraction numbers are off, and you enjoy that role
• You know when to escalate a layout-driven performance issue to the circuit designer and when to solve it yourself with a smarter floorplan or routing strategy

The Team You'll Be Part Of

You will be part of a strong development team focused on GPIO, specialty IO, and general-purpose analog IP development. The team works on a range of interface IP including I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG, high-performance LVDS, and crystal oscillators. You will collaborate closely with experienced engineers locally in Bangalore and across global sites, contributing to multi-site IP programs that serve customers worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.