Engineering Director - Subsystem Interoperability & AI-Driven Verification

Job Title: - Engineering Director - Subsystem Interoperability & AI-Driven Verification

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent two decades building verification teams and solving the problems that live between IP blocks, where clean interfaces meet messy reality and independently verified components refuse to cooperate. The gap between a Controller that passes all tests and a Controller-PHY-firmware combination that actually works in a customer SoC is where you live, and you have built the instincts to close it.

You are technical enough to review a UVM testbench, debug a protocol violation three layers deep, and make the call on whether a coverage hole is real or academic. But you also know that verification at scale is not about heroic debug sessions, it is about building systems that catch problems before they become customer issues. You think in factories, not fire drills.

What excites you now is applying AI to verification work that has resisted automation for years. You see LLMs, agentic workflows, and intelligent orchestration not as buzzwords but as tools that can finally turn interoperability from a bottleneck into a continuously running capability. You are ready to build that capability from the ground up at Synopsys, where the IP portfolio is real, the customer stakes are high, and the technical challenge is exactly the kind you have been preparing for.

What You'll Be Doing

• Build and lead the Central Interoperability team from scratch, defining its technical strategy, organizational structure, verification methodology, execution model, and success metrics across high-speed interface IPs including UCIe, PCIe, CXL, DDR, HBM, Ethernet, and USB
• Own end-to-end Controller-PHY interoperability qualification, from UVM environment bring-up and configuration management through verification execution, functional and structural coverage closure, protocol compliance, debug, and generation of customer-ready release evidence
• Establish an always-on Interop Factory where new Controller, PHY, or firmware releases automatically trigger integration, regression suites, qualification workflows, and evidence generation without manual intervention
• Drive interoperability verification beyond basic connectivity into protocol compliance, stress and error injection scenarios, CDC/RDC checks, timing constraints validation, and implementation readiness across the Controller × PHY × Firmware × VIP × Configuration state space
• Make the factory AI-native by applying LLMs, AI agents, RAG, MCP, and intelligent workflow orchestration to environment generation, test plan development, regression selection, failure clustering, root-cause analysis, debug acceleration, and knowledge reuse across releases
• Build a continuous learning loop where customer issues feed directly into root-cause analysis, prevention test creation, regression integration, and future release qualification, systematically converting field learning into improved product quality
• Partner across Controller and PHY R&D teams, architecture, VIP development, firmware, methodology, applications engineering, and product management to create one accountable, transparent subsystem-readiness view for every release

The Impact You Will Have

• You will create a new verification capability that shifts interoperability left in the development cycle, reducing subsystem bring-up time for customers and increasing the number of qualified Controller-PHY-firmware configurations available at release
• You will transform interoperability from a customer integration exercise into a continuously verified product capability, with reusable qualification evidence and clear release gates that reduce field issues and support escalations
• Your factory will establish a scalable blueprint for subsystem verification across the broader Synopsys IP portfolio, creating reusable infrastructure, methodology, and AI-enabled automation that other teams can adopt
• You will build a team culture that attracts top verification talent, mentors engineers into technical leadership roles, and keeps the organization technically engaged even as it scales
• You will make AI-assisted verification real and measurable, demonstrating how LLMs and agentic workflows can accelerate debug, improve coverage strategies, and turn tribal knowledge into reusable intelligence
• You will create predictable, data-driven subsystem readiness visibility for executives and customers, replacing subjective assessments with objective qualification metrics tied to real verification evidence
• You will reduce the time from IP release to customer-ready subsystem from months to weeks by automating the integration, qualification, and evidence-generation workflows that currently require manual coordination

What You'll Need

• 20+ years of semiconductor design and verification experience with significant technical leadership responsibility building and scaling verification teams
• Deep expertise in ASIC, SoC, IP, or subsystem verification using SystemVerilog, UVM, verification planning, functional and code coverage analysis, assertions, regression infrastructure, and complex multi-IP debug
• Strong hands-on experience with high-speed protocols such as UCIe, PCIe, CXL, DDR, HBM, Ethernet, USB, or SerDes, including protocol compliance, Controller-PHY integration, and interoperability challenges
• Proven track record integrating independently developed IP blocks and driving complex cross-functional technical programs across R&D, product, and applications teams
• Strong scripting and automation skills using Python, Tcl, or equivalent for building verification infrastructure, regression frameworks, and intelligent workflow orchestration
• Experience with CDC/RDC verification, formal methods, emulation or prototyping platforms, CI/CD for verification, or physical implementation flows is highly desirable
• Exposure to LLMs, agentic AI, RAG, MCP, AI-assisted verification or debug tools, or intelligent engineering automation is strongly preferred and will differentiate your application

Who You Are

• You can sit in a technical review with verification engineers debugging a CXL protocol failure and walk out with a clear action plan, then turn around and explain the customer-readiness risk to a VP in two sentences without losing the technical nuance
• You do not wait for perfect alignment across teams to get started, you define the interoperability strategy, build the initial environment, and prove the value before asking for full organizational buy-in
• You recruit engineers who are better than you at specific things and you create the conditions for them to do their best work, whether that is deep UVM expertise, AI automation, or protocol-level debug
• You have a point of view on what good verification looks like and you push back when a test plan is too shallow, a coverage model is missing critical scenarios, or a release gate is being bypassed without real justification
• You are energized by building new capabilities from scratch, not inheriting mature organizations, and you are comfortable with the ambiguity, cross-functional negotiation, and technical problem-solving that comes with that
• You stay technical, you still read code, review testbenches, understand coverage reports, and debug failures alongside your team, because that is how you earn credibility and make good decisions

The Team You'll Be Part Of

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