Senior Staff Engineer, Layout Design (Power & Analog ICs)

Job Description

We are seeking a Senior Staff Layout Design Engineer with deep expertise in analog and mixed-signal layout for power and analog IC products. This is a senior individual-contributor role requiring strong technical ownership, independent judgment, and the ability to lead layout execution for complex blocks and full-chip designs.

The successful candidate will translate circuit requirements into robust, manufacturable layouts for products such as PMICs, linear and switching regulators, gate drivers, battery-management ICs, and other power and analog devices. The role requires close collaboration with analog designers, CAD, process, package, reliability, and verification teams.

You will be expected to own challenging layout problems, establish best practices, improve methodology and automation, mentor engineers, and drive projects from floor planning through physical verification and tape-out readiness.

Responsibilities

Layout Architecture & Execution

• Own floor planning and physical implementation for complex analog, power, and mixed-signal blocks, and contribute to full-chip layout planning.
• Collaborate with circuit designers to capture electrical, matching, isolation, current-density, thermal, reliability, and area requirements.
• Apply advanced layout techniques for device matching, parasitic reduction, noise isolation, high-current routing, electromigration robustness, thermal behavior, and yield optimization.
• Drive routing, integration, and sign-off readiness for block-level and chip-level layouts.

Physical Verification & Sign-off

• Own and review DRC, LVS, ERC, PEX, antenna, density, latch-up, and reliability verification as required by the process and product.
• Analyse extracted parasitics with designers and support post-layout simulation closure.
• Identify physical-design risks early and drive corrective actions with design, CAD, PDK, process, and package teams.
• Ensure layout databases, review records, and release documentation meet tape-out quality standards.

Methodology, Automation & IP Reuse

• Develop and deploy automation using SKILL, TCL, Python, Perl, or similar languages to improve quality and turnaround time.
• Drive layout methodology improvements, reusable templates, checklists, and portability of IP across products and process technologies.
• Work with corporate engineering and CAD teams to resolve tool, PDK, extraction, and process-flow issues.
• Evaluate new layout tools and techniques and lead practical adoption within the team.

Technical Leadership & Mentorship

• Lead layout reviews and provide clear estimates, progress updates, risk assessments, and recovery plans.
• Mentor junior and mid-level layout engineers and raise the technical standard of the broader team.
• Influence project planning, task allocation, technical decisions, and hiring through demonstrated technical depth.
• Operate independently on ambiguous and complex assignments, escalating issues with clear options and recommendations.

Qualifications

• Bachelor or Masters degree in Electrical Engineering, Electronics Engineering, or a related discipline.
• 10+ years of relevant experience in analog, power, or mixed-signal IC layout and associated development flows.
• Demonstrated ownership of complex block-level layout and meaningful contribution to full-chip integration and tape-out.
• Deep understanding of matching, parasitic control, noise isolation, guard rings, latch-up prevention, high-current routing, electromigration, IR drop, thermal effects, and reliability-aware layout.
• Hands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre, PVS, or equivalent. Experience with extraction and reliability tools is expected.
• Experience working with deep-submicron CMOS and preferably BCD or high-voltage process technologies.
• Ability to automate layout or verification tasks using SKILL, TCL, Python, Perl, or similar scripting languages.
• Proven ability to lead technical reviews, mentor engineers, and drive layout methodology improvements.
• Strong cross-functional communication skills in a multisite and multicultural environment.
• Results-oriented, self-driven, and able to deliver high-quality work under tight schedules with limited supervision.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .