Principal PCS/PMA RTL Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Principal PCS/PMA RTL Design Engineer

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs.

You will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with SerDes/analog, verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation.

This is a hands-on opportunity for an engineer who wants to build expertise in multi-protocol, multi-lane PHY digital design and contribute to products that enable next-generation AI and cloud infrastructure.

Key responsibilities

PCS/PMA RTL design and implementation

• Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols.

• Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation.

• Implement forward error correction (e.g., RS-FEC/KP4, FEC framing, interleaving), plus the related error counters and status logic.

• Implement PMA digital interface logic, including SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), clock and data recovery (CDR) control interfaces, equalization and link-training control (e.g., PCIe LTSSM equalization, Ethernet auto-negotiation/link training), and calibration and adaptation control.

• Design lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation/checking, loopback modes, and BIST features.

• Translate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic.

• Design reusable, configurable RTL modules that support multiple protocols, data rates, and lane configurations.

• Integrate internal and third-party IP (including analog/mixed-signal PHY macros) while following established design and coding methodologies.

• Participate in design reviews and contribute to improvements in RTL quality, reuse, latency, performance, power, and area.

Verification and design quality

• Collaborate with design verification engineers to define functional requirements, test plans, and coverage goals, including protocol compliance (IEEE 802.3, PCI-SIG, UCIe, UALink specifications).

• Debug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis.

• Support lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and RTL quality checks, with particular attention to multi-clock-domain PCS/PMA boundaries and asynchronous lane clocks.

• Participate in UVM-based verification activities and help resolve functional and integration issues.

• Support gate-level simulation and regression debug as required.

Synthesis, timing, and implementation

• Support logic synthesis, constraints development, and design implementation flows for high-speed, wide-datapath designs.

• Perform Static Timing Analysis (STA) and help identify and resolve setup, hold, clock, and interface timing issues, including at the SerDes and PHY boundaries.

• Support timing closure, power optimization, and PPA trade-offs in collaboration with synthesis, timing, and physical-design teams.

• Assist with DFT integration, scan requirements, low-power intent (including per-lane power states), ECOs, and implementation signoff.

• Review reports and debug issues from Cadence and/or Synopsys digital design flows.

Silicon and cross-functional collaboration

• Support block-level and subsystem-level integration through tapeout milestones.

• Collaborate with SerDes/analog, physical design, DFT, firmware, systems, packaging, and validation teams.

• Participate in silicon bring-up, link bring-up, interoperability and compliance testing, post-silicon debug, and failure analysis as opportunities arise.

• Document design decisions, issues, and technical solutions clearly for cross-functional stakeholders.

Basic qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

• Master's degree is preferred.

• 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.

• Hands-on experience with Verilog or SystemVerilog RTL development.

• Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.

• Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer.

• Experience with RTL simulation, debugging, synthesis, and basic timing analysis.

• Familiarity with ASIC design flows and collaboration across design and verification teams.

• Strong communication skills and the ability to work effectively in a collaborative, fast-paced environment.

• Ability and willingness to work onsite in San Jose, California.

Preferred qualifications

• Direct experience designing PCS, PMA, or PHY digital logic for Ethernet (25G–224G per lane, 100G/200G/400G/800G/1.6T), PCIe (Gen4/5/6/7), UCIe, UALink, CXL, or similar standards.

• Experience with PAM4 signaling, FEC (RS-FEC/KP4, FLIT-mode FEC/CRC), lane deskew/alignment, link training, and equalization control.

• Familiarity with the PIPE specification, 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband.

• Experience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures.

• Familiarity with interconnect, networking, or data-center ASICs (retimers, switches, NICs, DPUs, SmartNICs, NoCs).

• Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.

• Experience with STA using tools such as Synopsys PrimeTime or Cadence Tempus.

• Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.

• Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.

• Experience with Python, Tcl, Perl, Shell, or other scripting languages for design and verification automation.

• Exposure to advanced-node CMOS design (e.g., 5nm/3nm), tapeout, silicon bring-up, or post-silicon validation, including BER measurements and lab debug.

• Experience working with physical-design teams on floorplanning, congestion, timing, power, and implementation challenges.

Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

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