P&R Implementation Senior Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of physical design, where the difference between a chip that tapes out and one that stalls in verification often comes down to a floorplan decision made weeks earlier or a timing path nobody caught until signoff. You know Fusion Compiler not as a tool you run, but as a platform you bend to solve real problems on real designs. You have closed timing on something that mattered, debugged a DRC violation that made no sense until it did, and optimized PPA on a block where every picosecond and microwatt counted.

Working with foundries does not intimidate you. You have navigated their PDKs, their design rules, their shifting timelines, and you understand that enablement is not about perfect flows, it is about flows that work when a customer has a tapeout date and no room for error. You ask the right questions when a testchip fails bringup, and you do not stop until you know why.

You are comfortable working across foundry teams, Synopsys product groups, and end customers, often in the same week. At Synopsys, you will work on advanced node testchips and 3DIC solutions that define what is possible at the edge of semiconductor technology.

What You'll Be Doing

• Drive foundry testchip projects from floorplan through tapeout, working directly with Synopsys advanced node enablement teams to validate new process technologies
• Develop and refine foundry implementation and 3DIC solutions aligned with Synopsys reference methodology, ensuring they work in real customer environments
• Provide hands-on engineering support to foundry partners and end customers on DTCO, PPA optimization, and testchip bringup challenges
• Debug complex P&R, timing, and physical verification issues using Fusion Compiler, PrimeTime, StarRC, IC Validator, and RedHawk across multi-die and advanced packaging contexts
• Coordinate with foundry partners, internal Synopsys product teams, and customer design teams to resolve implementation flow bottlenecks and drive adoption of Synopsys tools
• Collaborate with field account teams and foundry jumpstart teams to support mutual customer engagements and accelerate tool deployment
• Explore and integrate productivity improvements through automation, scripting, and AI-assisted engineering tools like Cursor to enhance design closure efficiency

The Impact You Will Have

• Enable successful tapeouts on advanced nodes by delivering high-quality physical design implementation for early testchips that validate new foundry processes
• Accelerate customer adoption of Synopsys Fusion Compiler and 3DIC solutions, directly influencing design wins and long-term tool loyalty
• Push the boundaries of what is achievable in Power, Performance, and Area through hands-on design optimization and methodology refinement
• Resolve critical design and flow issues that would otherwise block customer schedules, protecting revenue and strengthening foundry partnerships
• Shape the next generation of Synopsys reference flows by feeding real-world learnings back into product and methodology teams
• Mentor engineering teams across geographies, raising the technical bar for physical design execution and signoff quality
• Build trust with foundry partners and end customers by consistently delivering solutions that work under pressure and on schedule

What You'll Need

• Bachelor's or Master's in Electrical Engineering with 8+ years of hands-on physical design experience
• Deep expertise in place and route methodology, top-level implementation, and P&R timing signoff using Synopsys Fusion Compiler
• Proven experience in high-performance and low-power physical design, including full-chip PPA optimization and design closure
• Strong hands-on experience with physical design signoff tools such as PrimeTime, StarRC, IC Validator, and RedHawk or equivalent solutions
• Track record of contributing to real SoC, CPU, or GPU tapeouts, ideally on advanced nodes (7nm or below)
• Strong debugging and problem-solving skills, particularly in resolving complex timing, DRC, LVS, and IR drop issues
• Experience working with foundry PDKs and design rule decks is essential

Who You Are

• You approach a failing timing path or a stubborn DRC violation like a puzzle you will solve, not a problem you escalate
• You can sit in a meeting with a foundry engineer, a customer designer, and a Synopsys product manager and translate between all three without losing the technical thread
• You do not wait for a perfect flow to be handed to you, you build it, test it, and improve it based on what breaks
• You are comfortable owning a testchip block from floorplan to signoff, knowing when to dive deep and when to pull in the right expert
• You look at a design and see not just whether it closed, but whether it could close better, faster, or with less power
• You thrive in environments where the work is global, the stakes are high, and the problems are not always well-defined when you start

The Team You'll Be Part Of

You will be part of a dynamic and innovative team focused on developing cutting-edge foundry P&R implementation/3DIC/AI solutions with supporting foundry test chip projects. Our team collaborates closely with foundry partners, internal teams, and end customers to drive technological advancements and optimize implementation/3DIC flows. We value creativity, teamwork, and a commitment to excellence in all our projects.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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