Layout Design, Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have built a career in SRAM layout design, developing expertise in solving complex technical challenges at advanced process nodes where parasitic effects, density constraints, and matching requirements create significant design complexity. You understand that layout decisions made early in the design cycle have direct consequences for circuit performance, yield, and manufacturability, and you have developed the technical judgment to anticipate and address these issues systematically.

You work effectively with circuit design teams to translate design intent into physical implementation that meets stringent performance specifications. You bring both technical depth in memory layout and the ability to drive complex verification closure across multiple domains. At Synopsys, you will apply this expertise to memory compiler development that serves customers across the semiconductor industry, working within a team that values technical rigor and collaborative problem-solving.

What You'll Be Doing

• Lead physical layout development for embedded SRAM memory compiler peripheral circuits, including sense amplifiers, decoders, write drivers, and control logic across advanced technology nodes
• Optimize SRAM layouts to meet specifications for performance, power consumption, area efficiency, reliability, manufacturability, and yield
• Drive physical verification closure including DRC, LVS, ERC, antenna checks, and parasitic extraction, coordinating with CAD and verification teams to resolve technical issues
• Collaborate with circuit design teams to ensure layout implementations satisfy timing, matching, and electrical requirements
• Address advanced-node layout challenges including device matching, parasitic management, high-density routing, and reliability constraints
• Develop and implement layout methodology improvements and automation capabilities to enhance team productivity
• Provide technical guidance and mentorship to layout engineers, conducting design reviews and supporting skill development

The Impact You Will Have

• Your layout implementations will directly influence the performance, power, and area characteristics of SRAM compilers integrated into customer system-on-chip designs
• The methodologies and automation capabilities you develop will improve development efficiency and reduce time-to-market for future memory compiler releases
• Your technical contributions to verification closure and yield optimization will reduce risk and support program schedule adherence
• The technical leadership you provide will strengthen the capabilities of the layout engineering team and improve overall deliverable quality
• Your collaboration with circuit design and technology teams will support the successful adaptation of Synopsys memory IP to emerging process technologies
• Your design decisions will contribute to the competitive positioning of Synopsys memory solutions across key market segments
• Your work will enable reliable, high-performance embedded memory integration in applications spanning AI, automotive, mobile, and data center markets

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related technical discipline
• 6+ years of professional experience in SRAM or embedded memory layout design, including bitcells, arrays, and peripheral circuits
• Comprehensive understanding of SRAM architecture, including bitcell operation, array organization, sense amplifier design, and decoder/driver circuits
• Demonstrated ability to optimize layouts across multiple design objectives including performance, power, area, reliability, and manufacturability
• Strong analytical and problem-solving capabilities for complex layout challenges involving device matching, parasitic extraction, and advanced-node design rules
• Proven experience driving physical verification closure including DRC, LVS, ERC, and antenna checks
• Experience with scripting or layout automation is highly valued, as is experience with technology bring-up or foundry collaboration

Who You Are

• You possess strong technical judgment for identifying critical layout issues related to matching, routing, or parasitic effects and determining appropriate solutions
• You communicate effectively with circuit design teams regarding design feasibility, implementation tradeoffs, and potential technical risks
• You work productively in environments with evolving requirements and incomplete specifications, particularly during early technology node development
• You take ownership of technical deliverables and drive issues to resolution systematically
• You contribute to team development through mentorship and technical guidance, recognizing that collective capability strengthens overall execution

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.