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ASIC Design Engineer – Fabric/Interconnect

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Summary

At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy

Description

-Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).

Minimum Qualifications

Minimum of BS + 0 years relevant industry experience.

Preferred Qualifications

Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.

A consistent track record of delivering large, sophisticated designs in high volume production for low power applications

Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time

Strong interpersonal skills, as the candidate will work with diverse groups within the company

Self-starter, highly motivated, highly organized, and schedule driven

Familiarity with all front-end tools including lint, CDC, synthesis

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