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Synopsys

ASIC Digital Verification, Sr. Manager

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You Are:

You are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/SystemVerilog and are experienced in developing and managing testbenches in UVM environments. You are a natural leader with a proven track record of guiding and motivating teams to achieve their goals. Your expertise in high-speed interface protocols like PCIe/Ethernet and familiarity with IP design and verification tools positions you as an invaluable asset to any team. Your problem-solving skills, coupled with your ability to communicate effectively, enable you to navigate complex technical challenges and deliver high-quality solutions. You thrive in dynamic, multi-site environments and are driven by a passion for continuous learning and growth.

What You’ll Be Doing:

The Impact You Will Have:

What You’ll Need:

Who You Are:

The Team You’ll Be A Part Of:

You’ll join the Synopsys SERDES PHY IP team—a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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