Solutions Engineering, Staff Engineer DFT

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in DFT flows, the kind where a scan chain failure at 3 a.m. before tape-out is not a crisis, it is Tuesday. You know that DFT is not just about inserting scan cells and running ATPG, it is about making a chip testable in production, debuggable when it fails, and manufacturable at scale. You have debugged enough compression issues and hierarchical test mismatches to recognize the difference between a tool limitation and a setup mistake in about fifteen minutes.

You are the engineer who reads the DRC log, traces it back to the RTL, writes the Tcl workaround, and then explains to the customer why it happened and how to avoid it next time. You do not need perfect documentation to get started. You dig into waveforms, compare netlists, and work backward from silicon failures until you find the root cause. When a customer asks if something is possible, you do not guess, you build a test case.

You are comfortable sitting with a customer's DFT team in Shanghai one week and on a call with R&D in Mountain View the next, translating field requirements into product asks and product capabilities into working flows. At Synopsys, you will work on tools that test the chips that power everything, and the customers you support will remember your name because you helped them get to silicon.

What You'll Be Doing

• Own full customer DFT engagements from project kickoff through tape-out and first-silicon bring-up, covering scan compression, ATPG, XLBIST, OCC, IEEE 1687/1149, and hierarchical test flows
• Deliver hands-on technical training, workshops, and best-practice enablement sessions to customer DFT engineering teams across China
• Reproduce complex customer issues in-house, create minimal test cases, and partner with R&D to resolve product gaps, enhance features, and improve quality of results
• Support pre-sales technical evaluations and benchmarks, translating customer requirements into proof-of-concept flows using TestMAX, DFTMAX, and TetraMAX
• Write and maintain reusable enablement collateral including flow documentation, known issue summaries, and workaround guides for both internal teams and customers
• Debug DFT and ATPG issues using simulation, waveform analysis, and DRC/log file forensics to isolate root cause under tight schedule pressure
• Work across time zones with global R&D, sales, and customer teams, and travel to customer sites in China as needed for critical engagements

The Impact You Will Have

• Enable customers to tape out complex SoCs with robust, manufacturable test coverage, directly affecting yield and time-to-market for high-volume production chips
• Reduce customer debug cycles by catching DFT setup issues early and providing clear, actionable guidance that prevents downstream silicon failures
• Shape the product roadmap by translating field requirements and customer pain points into prioritized R&D feature requests and quality improvements
• Build customer confidence in Synopsys DFT solutions through hands-on enablement, responsive support, and deep technical credibility that drives tool adoption and renewals
• Accelerate time-to-resolution for critical issues by creating reproducible test cases and working directly with R&D to deliver fixes and workarounds faster than standard support channels
• Grow the knowledge base for the broader applications team by documenting flows, failure modes, and best practices that get reused across dozens of customer engagements
• Help customers successfully bring up first silicon by diagnosing scan chain failures, logic diagnosis mismatches, and ATE pattern issues that would otherwise delay production ramp

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 1+ years of hands-on DFT experience covering implementation, ATPG, or silicon test in a design or validation role
• Working knowledge of scan insertion, compression architectures, ATPG, OCC, IJTAG/IEEE 1687, and hierarchical DFT methodologies
• Proficiency with Verilog or SystemVerilog for reading RTL and netlists, and strong Unix/Linux command-line skills
• Scripting ability in Tcl, Python, or Perl to automate flows, parse logs, and build test environments
• Experience debugging DFT and ATPG issues using simulation tools, waveform viewers, and DRC/log file analysis to isolate root cause
• Strong written and verbal English communication skills, comfortable leading customer calls and writing clear technical summaries and reports
• Willingness to work across global time zones and travel to customer sites in China as needed for onsite engagements
• Experience with commercial DFT or ATPG tools such as Synopsys TestMAX, DFTMAX, TetraMAX, or equivalent platforms is a strong plus
• Silicon bring-up, ATE pattern validation, or diagnosis experience including scan chain failure analysis, logic diagnosis, or failure remapping is a plus
• Knowledge of static timing analysis for DFT modes, scan stitching, and at-speed test constraints is a plus

Who You Are

• You are a structured problem solver who can isolate root cause in a complex DFT flow under schedule pressure, working backward from symptoms to setup without getting lost in the noise
• You are comfortable sitting in a room with a customer's DFT team explaining why their compression ratio dropped, and then turning around and writing a clear bug report for R&D with a reproducible test case
• You do not wait for perfect information or complete documentation, you start with what you have, ask the right questions, and build a working flow while filling in the gaps
• You can explain a complex tradeoff between test coverage and pattern count to a customer engineering manager in two sentences without losing the technical nuance
• You are organized enough to manage multiple customer engagements in parallel, keeping track of open issues, follow-ups, and deliverables without dropping threads
• You are genuinely curious about why things fail, not just how to work around them, and you care about feeding that insight back so the product gets better

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.