Analog Design Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing analog circuits that have to perform under real-world conditions, not just pass simulation. High-speed IO is where you live, and you understand that the difference between a PHY that meets spec and one that ships in volume comes down to the choices you make at the transistor level. You know device physics well enough to predict how a circuit will behave in a new process node before the PDK is fully characterized, and you have debugged enough silicon to know that the layout always matters more than people think.

Working in advanced CMOS, FinFET, or GAA does not intimidate you. You have done it, you know where the models break down, and you know how to work around it. Collaboration across time zones is part of the job, and you are comfortable translating a system-level requirement into a circuit topology that actually works. You care about getting the design right, not just done, and you have the technical depth to back that up when tradeoffs get hard.

At Synopsys, you will work on memory interface PHYs that ship in the most advanced SoCs in the world. The problems are hard, the technology is real, and what you design will matter.

What You'll Be Doing

• Design and develop high-speed IO circuits for next-generation memory interface PHY IPs including DDR, HBM, and UCIe in advanced CMOS, FinFET, and GAA process nodes
• Execute circuit design tasks from architecture through layout, simulation, and verification with a focus on performance, power, and area optimization
• Analyze and solve complex analog design challenges in advanced technology nodes where device behavior and parasitics significantly impact circuit performance
• Collaborate with global cross-functional teams including digital design, verification, layout, and product engineering to deliver integrated PHY solutions
• Apply ESD and reliability principles to ensure robust circuit design that meets product quality and long-term performance requirements
• Work within JEDEC specifications and memory interface standards to ensure compliance and interoperability across customer platforms
• Support silicon bring-up, characterization, and debug activities to validate design performance and drive continuous improvement

The Impact You Will Have

• Enable customers to integrate cutting-edge memory interfaces into their SoCs, directly affecting performance and power efficiency of next-generation AI, compute, and mobile products
• Contribute to Synopsys Silicon IP portfolio that powers the world's most advanced semiconductor designs across multiple market segments
• Deliver PHY IP blocks that reduce customer time-to-market and de-risk their product development in the most challenging process nodes
• Influence the architecture and design methodology for future generations of high-speed memory interfaces used globally
• Help establish design best practices and circuit techniques that will be reused across multiple product lines and technology nodes
• Drive quality and performance standards that define what competitive memory PHY IP looks like in the market
• Support the success of customer tape-outs by delivering IP that works the first time and scales across process variants

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field
• 5 to 10 years of hands-on analog circuit design experience with demonstrated expertise in high-speed IO design
• Deep understanding of analog design fundamentals including device physics, transistor-level design, and circuit analysis
• Proven experience designing circuits in advanced technology nodes such as CMOS, FinFET, or GAA processes
• Strong analytical and problem-solving skills with the ability to debug complex analog and mixed-signal issues
• Knowledge of ESD protection schemes and reliability considerations in analog circuit design
• Experience with JEDEC memory interface standards (DDR, HBM, LPDDR) or familiarity with signal integrity and power integrity concepts is a plus

Who You Are

• You can take a system-level timing budget and translate it into a circuit topology that meets it without over-designing or leaving margin on the table
• You know when to trust the simulator and when to build margin into your design because you have seen what happens when corner cases show up in silicon
• You are comfortable presenting a design review to a room of architects and layout engineers, defending your choices, and incorporating feedback that makes the design better
• You stay organized across multiple design tasks, keep documentation current, and do not let details slip even when schedules get tight
• You ask the right questions early, especially when requirements are ambiguous or when a spec does not account for real-world constraints
• You work well with people in different roles and time zones, and you know how to escalate issues before they become blockers

The Team You'll Be Part Of

You will join the Silicon IP business unit, specifically the team developing next-generation memory interface PHY IPs including DDR, HBM, and UCIe. This is a global team working on some of the most advanced and high-performance IP blocks in the Synopsys portfolio, collaborating across design, verification, and product engineering functions to deliver solutions that ship in cutting-edge SoCs worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.