Sr Staff Engineer, FE-DFT and Timing Closure

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a front-end engineer who actually understands DFT, not just at the handoff level, but deep enough to know why a scan chain fails, why a compression ratio tanks, or why an ATPG tool chokes on certain RTL constructs. Most front-end engineers treat DFT as someone else's problem. You learned early that this creates expensive problems downstream, so you made it your business to understand both sides: clean RTL design and robust DFT implementation.

You know that R2G flow development lives or dies based on decisions made during front-end design. A poorly structured hierarchy, an ambiguous clock definition, or a missing constraint at the RTL level can break DFT insertion, formal verification, and timing closure all at once. You have debugged enough of these issues to spot them before they propagate, and you care enough to fix the root cause, not just patch the symptom.

At Synopsys, you will work with customers who need someone who can bridge the gap between front-end design intent and back-end DFT reality. What you build, guide, and standardize will determine whether their R2G flows actually work when it matters.

What You'll Be Doing

• Lead front-end design and DFT methodology development for customer SoC programs, ensuring RTL design decisions support robust DFT insertion and R2G flow execution
• Work directly with front-end design teams to establish DFT-aware coding practices, hierarchy planning, clock architecture, and constraint definitions that enable clean scan insertion and test coverage
• Deploy and support DFT implementation flows including scan insertion, compression, ATPG, and boundary scan across multiple customer programs
• Serve as the technical bridge between front-end design teams and back-end DFT, implementation, and verification teams, translating issues and requirements in both directions
• Debug complex DFT failures that trace back to RTL design decisions, tool interpretation differences, or constraint mismatches, and drive resolution across teams
• Develop and standardize R2G flow methodologies that integrate front-end design quality checks with DFT readiness and back-end implementation requirements
• Support risk mitigation and schedule recovery for programs where front-end and DFT integration issues are blocking progress

The Impact You Will Have

• Customer R2G flows execute cleanly because the front-end design was built with DFT requirements baked in from the start, not bolted on later
• DFT insertion and ATPG convergence accelerates across programs because you caught and fixed RTL issues that would have caused failures weeks downstream
• Front-end teams adopt DFT-aware design practices that prevent entire classes of scan, compression, and timing issues from ever appearing
• Cross-functional teams resolve front-end and DFT integration problems faster because you can speak both languages and translate the real issue
• Program schedules stay on track because you identified where the RTL and DFT flow were misaligned and built a methodology fix that worked
• Synopsys R2G flows and best practices improve because you fed real customer pain points back with enough technical depth to drive methodology and product enhancements

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience in SoC design
• 10+ years of hands-on experience in front-end RTL design, with significant exposure to DFT implementation, scan insertion, ATPG, or test methodology
• Strong understanding of DFT concepts including scan chains, compression, ATPG, boundary scan, and how RTL design decisions impact test coverage and flow execution
• Proven ability to debug complex issues that span front-end design, DFT insertion, and back-end implementation, often involving multiple EDA tools
• Experience developing or deploying R2G flows that integrate front-end design quality, DFT readiness, and back-end implementation requirements
• Ability to work across cross-functional teams and communicate technical issues clearly to both design and DFT engineers
• Experience working directly with customers or internal product development teams in a technical lead or applications engineering capacity is a strong plus

Who You Are

• You are the front-end engineer who actually reads the DFT engineer's bug report instead of forwarding it, because you know you can probably fix it faster if you understand what broke
• When a scan insertion fails, you do not just blame the tool, you open the RTL, check the hierarchy, and figure out what the design is doing that the tool cannot handle
• You think about testability while you are writing RTL, not as an afterthought, because you have debugged enough late-stage ATPG failures to know the cost of ignoring it
• You can sit in a room with a front-end design lead and a DFT lead who are talking past each other, and translate the issue into terms both can act on
• You stay calm when a program is stuck between front-end signoff and DFT insertion, because you have been there before and you know how to find the real blocker
• You build methodology fixes, not one-off workarounds, because you want the next program to avoid the problem entirely

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.