Architect - Subsystem Interoperability & AI-Driven Verification

Job Title : - Architect - Subsystem Interoperability & AI-Driven Verification

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a recognized technical leader who thinks in systems, not individual IP blocks. You understand where interoperability challenges emerge at architectural boundaries, configurations, initialization sequences, protocol interactions, firmware dependencies, clock and reset domains, implementation constraints and assumptions made between independently developed IP. Deep hands-on verification expertise combines with your ability to define technical strategy, influence architecture, and lead engineering transformation across organizational boundaries. You are equally comfortable defining a subsystem verification architecture, reviewing SystemVerilog/UVM environments, analyzing coverage, debugging a challenging Controller-PHY interaction in Verdi, developing automation in Python and presenting technical direction to senior R&D leadership. You don't simply debug interoperability problems. You architect them out of the system. The most complex cross-IP technical investigations energize you because solving them well means preventing entire classes of failures before they reach customers. At Synopsys, you will help build the next generation of subsystem interoperability verification across high-speed interface IPs, and you will pioneer how GenAI, LLMs, and agentic workflows transform verification from reactive debugging into continuous intelligent qualification.

What You'll Be Doing

• Define the technical vision for subsystem interoperability spanning Controller, PHY, firmware, VIP, verification environments, and customer configurations across multiple high-speed interface IP families
• Architect a scalable Interop Verification Platform that enables continuous integration, verification, and qualification across IP releases, solving the configuration challenge across Controller × PHY × Firmware × VIP × Protocol Mode × Customer Configuration using intelligent risk and coverage-based qualification
• Establish reusable verification architectures, methodologies and golden reference environments covering functional verification, protocol compliance, error and stress scenarios, coverage, assertions, CDC/RDC and system initialization
• Lead the most complex cross-IP technical investigations and drive systemic solutions across RTL, PHY, firmware, VIP, testbench and implementation boundaries when interoperability issues surface
• Partner with Controller and PHY architects and R&D teams to influence interfaces, observability, design-for-verification and subsystem architecture early in the development lifecycle
• Pioneer an AI-native verification architecture that applies GenAI, LLMs, RAG and agentic workflows across the verification lifecycle: specification to verification intent to environment to tests to regression to debug to qualification to learning
• Architect AI-assisted generation of environments and tests, intelligent regression selection, automated log and failure clustering, coverage-gap analysis, protocol and waveform debug, root-cause recommendations, engineering knowledge retrieval and automated qualification evidence

The Impact You Will Have

• Transform interoperability from a late-stage integration activity into a continuous product capability that accelerates subsystem bring-up and qualification across Synopsys IP portfolios
• Scale verification across increasingly complex IP configurations, enabling Synopsys to deliver subsystems that work together seamlessly before they reach customer environments
• Convert field issues into permanent prevention tests and reusable engineering knowledge, reducing repeat failures and building institutional memory into the verification platform
• Establish common interoperability methodology across multiple IP families including UCIe, PCIe/CXL, Ethernet, DDR/HBM, USB and AMBA/CHI, creating consistency and reuse across product lines
• Create an AI-native verification architecture capable of scaling engineering expertise across products and organizations, fundamentally changing how Synopsys qualifies complex subsystems
• Define compatibility matrices and qualification criteria that provide clear, evidence-based confidence that a specific Controller-PHY combination is customer ready, reducing integration risk and time-to-market
• Mentor senior engineers and serve as a technical authority for subsystem interoperability, raising the bar for verification excellence across the organization

What You'll Need

• 15+ years of ASIC/IP/SoC verification experience with demonstrated technical leadership on complex verification programs where you defined architecture, influenced direction, and delivered results across organizational boundaries
• Deep expertise in SystemVerilog, UVM, assertions, functional and code coverage, verification closure and complex debug, with hands-on experience building and reviewing sophisticated verification environments
• Proven experience architecting reusable verification environments for IP, subsystem or SoC designs that scaled across multiple projects or product lines
• Strong expertise in one or more high-speed protocols such as UCIe, PCIe/CXL, Ethernet, DDR/HBM, USB or AMBA/CHI, with deep understanding of protocol interactions, initialization sequences, and interoperability challenges
• Hands-on expertise with industry-standard simulation and debug tools, VIP and coverage infrastructure, specifically VCS and Verdi or equivalent toolchains
• Strong automation expertise in Python, Tcl or equivalent scripting languages, with a track record of building tools that improve verification productivity
• Experience with CDC/RDC, formal verification, emulation/prototyping, CI/CD or distributed verification infrastructure is highly desirable, as is experience or strong interest in GenAI, LLMs, RAG, agentic AI and AI-assisted verification

Who You Are

• You can walk into a room where a Controller-PHY integration is failing in a customer configuration, debug the waveforms in Verdi, identify the root cause across firmware, RTL and protocol assumptions, and define the systemic fix that prevents similar issues across all future configurations
• You influence technical direction and align teams without relying on organizational authority, using technical credibility, clear communication and a track record of solving hard problems to drive consensus
• You mentor senior engineers by showing them how to think about verification architecture, not just how to write better tests, raising the technical bar for everyone around you
• You balance deep technical work with strategic thinking, moving fluidly between reviewing a UVM testbench, defining a three-year verification roadmap, and presenting technical direction to R&D leadership
• You see AI and LLMs not as hype but as tools that can fundamentally change how verification scales, and you are ready to architect how GenAI integrates into the verification lifecycle from specification to qualification
• You push back when an interface design creates unnecessary interoperability risk or when a qualification plan lacks evidence, because you care more about building systems that work than making everyone comfortable

The Team You'll Be Part Of

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