SOC Architect

About Rivian

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Role Summary

Help shape the silicon behind the next generation of electric mobility. Rivian is building products and services that help people explore, experience, and move through the world more sustainably. As a SoC Architect, you will help define the compute platforms that enable Rivian’s next generation of electric vehicles and connected experiences.

You will own key parts of automotive system-on-chip architecture, from early product definition through implementation and production. Working across hardware, software, systems, functional safety, security, and silicon engineering, you will translate vehicle requirements into scalable, power-efficient, production-ready compute solutions.

This senior individual-contributor role is for an architect who can move comfortably between system-level strategy and detailed technical decisions. You will influence teams across the organization, bring clarity to complex programs, and help turn ambitious ideas into robust products.

A strong candidate is energized by difficult, ambiguous problems and comfortable making high-quality decisions with incomplete information. They combine systems thinking with technical depth, communicate directly, seek diverse perspectives, and stay close enough to implementation to ensure that architecture delivers real product value.

They are self-directed and proactive. They look for important problems to solve, take ownership from definition through execution, and help teams move forward when requirements or constraints are still evolving.

Responsibilities

• Define and evolve SoC and compute-platform architectures for automotive applications, including compute, memory, interconnect, I/O, and system integration.

• Translate vehicle, platform, software, and customer requirements into clear architectural specifications and measurable design goals.

• Lead tradeoff decisions across performance, power, cost, area, thermal constraints, reliability, schedule, and product scalability.

• Define partitioning strategies across CPUs, NPUs, DSPs, accelerators, safety islands, and other heterogeneous compute resources.

• Define memory hierarchies, cache-coherency models, interconnect fabrics, bandwidth budgets, and data-movement strategies for demanding vehicle workloads.

• Partner with silicon design, verification, physical design, firmware, operating-system, embedded-software, validation, and systems teams to move architecture into implementation.

• Establish performance models, workload assumptions, benchmarks, and analysis methods to validate architectural decisions early.

• Incorporate functional safety, cybersecurity, reliability, diagnostics, and fault-containment requirements throughout the architecture.

• Review and guide third-party IP selection, integration, and qualification where appropriate.

• Identify technical risks, close architectural gaps, and communicate decisions and tradeoffs to technical and executive stakeholders.

• Contribute to architecture roadmaps and reusable platform strategies across multiple vehicle programs and product generations.

• Mentor engineers and improve architecture practices, documentation, technical reviews, and decision-making across the organization.

Within your first year, you will have:

• Built trusted technical partnerships across silicon, software, systems, safety, security, and vehicle engineering.

• Defined or materially advanced a SoC architecture aligned with Rivian’s product and platform roadmap.

• Created a clear, data-backed framework for evaluating performance, power, memory, and scalability tradeoffs.

• Reduced architectural risk by identifying critical dependencies and validating high-impact assumptions early.

• Helped establish a repeatable architecture practice that enables faster, higher-confidence decisions across future programs.

• Built an effective working relationship with silicon partners through clear, timely, and technically strong communication.

Qualifications

Candidates should meet at least four or five of the qualifications below, along with a strong record of technical ownership and impact.

Required

• Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related technical field.

• 8+ years of experience in SoC, ASIC, CPU, accelerator, or complex embedded-system architecture and development.

• Demonstrated experience taking complex silicon or compute-platform architectures from concept through implementation and production.

• Strong understanding of computer architecture, memory systems, cache coherency, interconnects, virtualization, and hardware/software interfaces.

• Experience with heterogeneous compute architectures and workload-driven performance analysis.

• Ability to reason quantitatively about performance, power, bandwidth, latency, area, and system-level constraints.

• Experience across the silicon development lifecycle, including architecture, design, verification, bring-up, and post-silicon validation.

• Strong written and verbal communication skills, with the ability to explain complex technical decisions to both specialist and cross-functional audiences.

• Experience with hardware-security architecture, secure boot, trusted execution, isolation, key management, and threat-informed design.

• Track record of influencing outcomes without relying on direct organizational authority.

Preferred qualifications

• Experience designing SoCs or compute platforms for automotive, robotics, mobile, aerospace, industrial, or other safety- or reliability-critical products.

• Familiarity with automotive functional-safety concepts and standards such as ISO 26262.

• Experience with camera pipelines and image processing.

• Experience with radar-processing DSP architectures.

• Experience with ARM or RISC-V CPU architecture.

• Experience with high-speed I/O, such as PCIe, Ethernet, UFS, and MIPI interfaces.

• Experience with high-performance interconnect standards, chiplet-based systems, advanced packaging, or multi-die architectures.

• Experience building architectural simulators, performance models, emulation environments, or workload-analysis tools.

• Knowledge of low-power design techniques, thermal management, clock and power domains, and automotive-grade reliability requirements.

• Experience collaborating with semiconductor vendors, IP providers, foundries, or external engineering partners.

Pay Disclosure

The salary range for this role is $237,000 - $312,000 for Palo Alto, CA based applicants and $192,000 - $275,000 for Austin, TX based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for annual performance bonus and equity awards.

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