Lead Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal Application Engineer (Front-end Verification)

Position Description:

• Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
• Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
• Train, ramp-up and accompany customer project.
• Conduct basic and advanced trainings, presentations and demos as necessary.
• Providing technical expertise to address clients’ queries, which need expert involvement.
• Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:

Over 2~8 years’ experience in the following areas:

• 2.Design experience in Verilog/VHDL for IP or SoC chip level.
• HW verification with knowledge of System Verilog/VHDL and HDL simulators
• FPGA prototyping project experience
• Experience with hardware emulator or accelerator is a big advantage
• Advanced Verification Methodology like UVM is a plus
• Knowledge of Unix and Linux is highly desired
• Strong verbal and written communication skills in English
• Strong teamwork skills with good human relationship

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