High Speed IP PHY/USB Applications Principal Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in ASIC design and verification, and somewhere along the way you realized that the most satisfying part of the work is not just getting the design right, it is helping someone else get their design right. You enjoy isolating root causes, asking the right questions, and driving issues to closure under tapeout pressure. You can work across the ASIC flow (synthesis, CDC, STA constraints, bring-up debug) and communicate clearly with both architects and implementation teams.

What You'll Be Doing

• Provide technical support to customers integrating DesignWare USB Mixed Signal PHY IP as the primary focus, from initial integration through silicon bring-up and debug
• Troubleshoot customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing in USB PHY and SoC integration contexts
• Guide customers through USB 2.0, USB 3.x, and Type-C implementation considerations and design tradeoffs, and help define bring-up and debug plans that reduce time-to-silicon
• Collaborate closely with the Korea AE team and Synopsys R&D and product teams to escalate complex issues, drive root-cause analysis, and ensure timely closure during critical milestones
• In addition to USB, contribute to customer support coverage for other high-speed interface PHY IP in collaboration with colleagues, leveraging similar integration and debug fundamentals (e.g., MIPI, PCIe, HDMI, etc.; excluding DDR)
• Deliver technical presentations and integration best practices to customer engineering teams during design reviews and key program checkpoints
• Travel occasionally to customer sites across Korea and the region to support critical milestones

The Impact You Will Have

• Enable customer success on high-stakes tapeouts by resolving USB PHY integration issues that would otherwise delay schedules
• Reduce time-to-silicon by providing clear, actionable guidance during integration, constraints closure, and silicon bring-up
• Build deep technical relationships with leading semiconductor companies in Korea as their trusted advisor
• Shape future IP releases by channeling real customer pain points back into the product team
• Expand Synopsys footprint in customer accounts through technical depth, responsiveness, and cross-team collaboration

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10 to 20+ years of ASIC design, verification, or SoC integration experience
• Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing
• Ability to work independently and drive ambiguous, customer-driven issues to resolution
• Excellent communication skills in Korean and English, able to explain complex concepts clearly
• USB 2.0, USB 3.x, Type-C, or USB PHY integration experience is a strong plus
• Broader high-speed interface background (e.g., MIPI, PCIe, HDMI) is a plus and helps with collaborative cross-IP support coverage
• Willingness to travel occasionally within Korea and the region

Who You Are

• You can take a vague customer complaint and within two questions know whether it is a constraint issue, integration problem, or something else
• You are comfortable saying 'I do not know, but I will find out' and then actually following through
• You know when to pull in the right specialist from R&D and how to frame the problem so they can help
• You can explain a complex tradeoff to a customer architect in two sentences without losing the nuance
• You see customer edge cases as opportunities to improve, not complaints to deflect