Staff Engineer, Memory Layout Design

Memory Layout, Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of custom layout, and somewhere along the way you realized the real leverage is not in drawing one more SRAM cell, it is in building the frameworks that let hundreds of those cells get generated correctly, verified automatically, and scaled to the next node without reinventing everything. You think in systems, not schematics. When you look at a new process node, you are already mapping out the design rules, the automation gaps, and the verification bottlenecks before anyone asks.

You are the engineer who gets called when a layout flow breaks at 3nm or when a compiler needs to scale and no one is sure how to get StarRC and Custom Compiler to play nicely together. You do not just script solutions, you architect them with an eye toward maintainability, reuse, and the next three nodes. You have strong opinions about what good automation looks like, and you are not afraid to push back when a methodology does not serve the people who will actually use it.

At Synopsys, you will define how next-generation embedded memory gets built, not by drawing it yourself, but by creating the infrastructure that makes it possible for teams across the company to do it faster, cleaner, and more reliably.

What You'll Be Doing

• Lead technology studies and process entitlement evaluations for advanced nodes (FinFET, GAA) to define what is physically possible and translate that into actionable layout guidelines for embedded memory compiler teams
• Architect and build layout automation frameworks using Python and TCL that generate, verify, and validate custom memory IP layouts at scale, not one-off scripts but production infrastructure
• Develop and maintain automated physical verification flows integrating Synopsys Custom Compiler, StarRC for parasitic extraction, and Ansys Totem for EM/IR reliability analysis across memory compiler products
• Author and document physical implementation design rules, best practices, and layout methodologies that become the standard for how SRAM, ROM, and register file compilers are built and scaled
• Evaluate next-generation EDA tools and capabilities, working directly with vendors and internal teams to define what gets adopted, how it gets integrated, and what productivity gains are realistic
• Provide technical leadership and mentorship to layout development teams, troubleshooting complex verification failures, flow bottlenecks, and tool integration issues that block progress
• Collaborate with foundry partners on design-technology co-optimization, feeding real-world layout constraints and automation needs back into process development discussions

The Impact You Will Have

• Enable Synopsys memory compiler teams to scale to next-generation nodes faster by defining clear, automated methodologies that eliminate guesswork and rework
• Reduce time-to-market for embedded memory IP by building verification and extraction flows that catch issues early and run without manual intervention
• Improve layout productivity across the organization by delivering automation tools and infrastructure that teams actually use and trust
• Influence foundry roadmaps and EDA tool development by representing real custom layout challenges and methodology needs in co-optimization discussions
• Establish the technical standard for how advanced memory architectures are physically implemented, verified, and delivered at Synopsys
• Mentor and elevate layout engineers by providing them with better tools, clearer guidelines, and a methodology framework that scales with their work
• Drive reliability and quality improvements by automating EM/IR analysis and parasitic extraction in ways that surface problems before tapeout

What You'll Need

• 8+ years of hands-on experience in custom IC layout methodology, EDA automation, or physical design enablement, with a strong focus on embedded memory architectures like SRAM, ROM, or register files
• Deep proficiency in Python and TCL for building production-grade layout automation tools, verification flows, and EDA infrastructure, not just scripting but software development
• Extensive experience developing and deploying automated physical verification flows using Synopsys Custom Compiler, StarRC, Ansys Totem, or equivalent industry-standard tools
• Solid understanding of advanced process nodes (FinFET, GAA, 5nm and below) and the ability to translate complex foundry design rules into engineering guidelines and automation requirements
• Strong working knowledge of DRC/LVS/Antenna checking, EM/IR drop analysis, and parasitic extraction methodologies in the context of full-custom layout
• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Science, or related field with a focus on EDA or layout methodology
• Experience collaborating with foundry teams on design-technology co-optimization or familiarity with AI/ML frameworks for automating engineering tasks is a strong plus

Who You Are

• You can walk into a room with a process design kit and walk out with a methodology roadmap that accounts for layout complexity, tool limitations, and team bandwidth
• When a verification flow fails in a way no one has seen before, you do not escalate immediately, you dig into the tool logs, reproduce the issue, and figure out what broke and why
• You write automation code that other engineers can actually read, maintain, and extend six months later without needing you to explain every function
• You have a point of view on what good layout methodology looks like and you are comfortable defending it in a room full of senior engineers who may not agree
• You can explain a complex tradeoff between layout density, verification runtime, and EM reliability to a product manager in two sentences without losing the technical nuance
• You stay current on EDA tool capabilities, process technology trends, and automation techniques because you know that what worked at 7nm will not necessarily work at 3nm

The Team You'll Be Part Of

You will join the Memory Layout Methodology and Automation team in Noida, a group responsible for defining how embedded memory compilers are physically implemented, verified, and scaled across Synopsys IP products. This is a technical leadership role where your work directly shapes the infrastructure and guidelines that memory development teams rely on to deliver next-generation SRAM, ROM, and register file IP to customers.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.