Mixed-Signal Verification Engineer

Summary

Every pair of AirPods carries a wireless chip our team verified — we’ve done it since the very first one. We also verified Apple’s N1 wireless chip, which powers connectivity across every new iPhone, and its successor is already taking shape. Our organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level. In the Mixed-Signal DV team, we model and verify the analog and RF heart of Apple’s wireless silicon: radios, data converters, PLLs, power management and clock distribution. We prove it all works together before tape-out. If you like understanding circuits and systems, and then putting them to the test in simulation, you’ll fit right in.

Description

As a mixed-signal design verification engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with analog/RF design, SoC DV/design, PHY DV/design, power management DV/design and wireless system teams. You will use best-in-class verification methodologies (including GenAI) that ensure silicon-correct functionality with optimal coverage and time-to-tapeout trade-off. You’ll own an area with real autonomy and support. We believe in learning by doing — you’ll build depth in your own specialties and breadth across the chip, project to project, in a dynamic design environment driven by new product needs.

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience

Industry verification experience with RF/mixed-signal blocks and SoCs

Hands-on experience building mixed-signal testbenches, checkers and tests using SystemVerilog

Strong verification skills in critical thinking, problem solving, testing, and debugging

Solid understanding of analog/RF circuits such as PLLs, ADCs, RX/TX chains or power delivery

Great communicator and team collaborator; self-motivated, organized, and eager to take on diverse challenges

Preferred Qualifications

Masters or PhD degree in technical disciplines with at least 5+ years of hands-on relevant experience

DMS verification experience

Wireless silicon experience

Hands-on experience creating and using real-number analog behavioral models in SystemVerilog

Interest in applying GenAI to verification, modeling or debug

Experience with UVM methodology

Experience with UPF, Python or Matlab

Experience with Virtuoso Composer, ADE, and HED