SoC UPF Methodology Engineer

Summary

Are you passionate about crafting solutions to intricate challenges? Join the Low Power group

at Silicon Technologies and contribute to the development of cutting-edge technology and

capabilities for low-power chip design. Your work will fuel Apple’s next-generation chips!

You’ll play a crucial role in exploring AI/ML to design the workflow for the next generation of

UPF. Additionally, you’ll refine our existing UPF framework and ensure its seamless integration

and rigorous verification across our mobile products.

You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.

We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs.

Description

In this role, your main objective will be to enhance our Unified Power Format (UPF)

methodologies, refining power intent specification, execution, and validation to support state-

of-the-art mobile SOCs. Key responsibilities encompass:

• Enhancing power intent coverage via advanced static and dynamic verification techniques.
• Developing tailored UPF solutions to align with unique project requirements.
• Overseeing UPF deployment and sign-off for frontend (FE) and place-and-route (P&R) stages.
• Conducting thorough power intent assessments on custom circuitry.
• Partnering with design and verification teams to troubleshoot and fix UPF-related workflow

challenges.

• Integrating AI/ML technologies to optimize UPF processes and methodologies.

Minimum Qualifications

A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience

Preferred Qualifications

Expertise in UPF implementation and verification.

Proficiency in scripting with languages like Python and Tcl.

Understanding of CMOS power design principles.

Experience applying AI/ML to coding and workflow optimization.

Knowledge of multi-voltage static verification tools (e.g., VSILP/VCLP, CLP).

Familiarity with the complete RTL-to-GDSII design flow.

Strong communication abilities for effective collaboration across multidisciplinary teams.