SerDes Analog Design & Correlation, Principal Engineer - 18617

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary and detail-oriented analog designer, passionate about high-speed SerDes circuits and how they truly behave in silicon. With a deep foundation in transistor-level design, you translate specifications into robust, scalable circuits, balance power, area, and performance trade-offs, and anticipate the parasitics, mismatch, and process variation that separate simulation from reality.

You believe a design is not finished until simulation explains silicon. When measurements disagree with expectations, you define what needs to be measured and why, refine your models until the gap is understood, and trace it back to the circuit, the layout, the device models, or the package and channel. You work closely with validation engineers, guiding test plans and interpreting their data, and you feed every lesson into the next design revision and into the team’s methodology. You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you are excited to make a lasting impact at Synopsys.

What You’ll Be Doing:

• Own the design and implementation of analog macros for SerDes IP across the TX, RX, CDR, and clock paths.
• Interpret SerDes standards and architecture documents to develop detailed macro specifications.
• Optimize circuits for power, area, and performance, and oversee layout to minimize parasitics, device stress, and process variation impacts.
• Propose and execute design verification strategies using advanced simulator features, including corner and Monte Carlo analysis.
• Collaborate with digital RTL engineers on calibration, adaptation, and control algorithms for your circuits.
• Define the sim-to-silicon correlation plan for your macros, specifying what to measure, under which conditions, and why.
• Build and refine models, including extracted parasitics, behavioral models, and channel/S-parameter models, until simulation explains silicon.
• Root-cause gaps between simulation and silicon back to circuit, layout, device modeling, or package and channel effects.
• Partner with the validation team to guide test plans and interpret measurement data, feeding fixes into the next design revision.
• Mentor a small group of analog designers, and present design and correlation results for peer and customer reviews.

The Impact You Will Have:

• Deliver silicon-proven analog macros that elevate the performance and reliability of Synopsys’ industry-leading SerDes IP.
• Close the loop between simulation and silicon, improving model accuracy and first-pass silicon success.
• Prevent costly respins by catching modeling and design gaps before the next tapeout.
• Strengthen design methodologies so that lessons from silicon carry into future product generations.
• Accelerate time-to-market for next-generation PCIe and Ethernet IP.
• Give customers confidence through clear, data-backed explanations of silicon performance.
• Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

What You’ll Need:

• MSc with 8+ years, or PhD with 6+ years of SerDes/high-speed analog design experience, including sim-to-silicon correlation of silicon-proven designs.
• Expertise in transistor-level circuit design, with silicon-proven TX, RX, and clock-path circuits in SerDes architectures.
• In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
• Experience with analog behavioral modeling using Verilog-A.
• Strong understanding of device modeling and process variation, and their impact on circuit performance.
• Experience with link and channel analysis, including S-parameter and package models.
• Familiarity with high-speed link measurements and the ability to interpret lab data statistically.
• Proficiency with EDA tools and SPICE simulators, including parasitic extraction, corner, and Monte Carlo analysis.
• Programming experience in TCL, Perl, C, Python, and MATLAB for design automation, modeling, and data analysis.

Who You Are:

• Analog designer at heart who insists that simulation explains silicon.
• Analytical thinker who digs deeper when the data does not make sense.
• Pushes back when root cause stops at correlation instead of causation.
• Collaborative partner to validation, layout, and modeling teams.
• Effective communicator who turns data into clear design recommendations.
• Mentor and technical lead for junior designers.
• Committed to excellence, reliability, and continuous improvement.

The Team You’ll Be A Part Of:

You will join a dynamic and multidisciplinary team of analog, digital, mixed-signal, and validation engineers dedicated to developing industry-leading SerDes IP solutions. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly shape how each generation of IP is designed, modeled, and proven in silicon. Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise will have a direct impact on both product and team success.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.