SOC Engineering, Sr Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of physical design, working on silicon that actually tapes out and ships in products people use. You know that the difference between a PHY that meets timing and one that doesn't often comes down to decisions made during floorplanning, and you are the kind of engineer who sees those decisions coming. You have worked with ICC2 and FC long enough to know their quirks, their strengths, and when to push back on a flow that isn't going to scale. FinFet brought new challenges, and you learned to navigate them not by reading whitepapers but by closing designs under real constraints.

When a project hits a wall at 48 hours before tapeout, you are the person others turn to. Not because you panic less, but because you have seen enough crises to know what actually matters and what is noise. You can walk into a room with a customer team, explain a tradeoff in two sentences without losing the technical nuance, and walk out with alignment. You do not wait for perfect specs. You work with what you have, ask the right questions, and move. At Synopsys, you will work on DDR and HBM PHYs that power the memory subsystems in chips across industries, and the work you do will be tested in real silicon.

What You'll Be Doing

• Implement DDR and HBM PHYs for customer ASICs and SOCs, taking designs from RTL through physical implementation, timing closure, and signoff
• Run synthesis, place and route, and physical verification using ICC2, Fusion Compiler, and ICV on advanced FinFet nodes
• Perform design for test insertion and ATPG, ensuring manufacturable and testable designs
• Serve as the technical lead on design engagements, coordinating with internal Synopsys teams and external customer design teams to deliver on schedule
• Provide regular project updates to management and front customer-facing communication on technical progress, risks, and mitigation plans
• Debug complex timing, power, and physical design issues across multi-million gate designs, often under tight tapeout schedules
• Guide junior engineers on physical design methodology, tool usage, and best practices for closure on advanced nodes

The Impact You Will Have

• Deliver DDR and HBM PHY IP that meets performance, power, and area targets for customer chips shipping in high-volume production
• Reduce project risk by catching design issues early and proposing solutions that keep schedules on track
• Strengthen customer relationships through reliable execution and clear technical communication during critical project phases
• Improve internal design flows and methodologies by contributing lessons learned from real tapeouts back into the team's knowledge base
• Accelerate the growth of junior engineers by providing hands-on mentorship on complex physical design challenges
• Expand Synopsys' reputation as a trusted partner for memory subsystem design services in the semiconductor industry
• Enable faster time-to-market for customer products by delivering high-quality, first-pass-correct PHY implementations

What You'll Need

• 5+ years of hands-on experience in ASIC physical design, with multiple successful tapeouts on advanced nodes
• Deep working knowledge of Synopsys tools including Design Compiler, PrimeTime, ICC2 or Fusion Compiler, and ICV
• Experience implementing designs on FinFet process technologies (7nm, 5nm, or below)
• Proven ability to close timing, power, and signal integrity on complex, high-speed interface designs
• Strong debugging skills across the physical design flow, from synthesis through signoff
• Experience with DDR or HBM PHY design is a strong plus
• Familiarity with design for test methodologies and ATPG tools is a plus

Who You Are

• You can take a failing timing path at 3am and figure out whether it is a floorplan issue, a constraint issue, or a synthesis problem, and you know which one to fix first
• You communicate technical tradeoffs clearly to both engineers and customers, without jargon when it is not needed and with precision when it is
• You have managed multiple priorities under tight deadlines and know how to triage what needs attention now versus what can wait
• You are comfortable working across time zones with distributed teams, and you adapt your communication style to keep everyone aligned
• You take ownership of problems even when they cross tool boundaries or team boundaries, and you follow through until they are resolved
• You learn new tools and methodologies quickly, not because you memorize commands but because you understand the underlying principles

The Team You'll Be Part Of

You will join the DDR and HBM PHY Hardening service line, a team that partners directly with customers to implement memory PHYs for their most critical chip programs. The team works across the full physical design flow and collaborates closely with Synopsys IP and EDA product teams. Your recruiter will share more about the team structure and current project portfolio during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.