Junior SI/PI and Packaging Engineer

The SIP (Signal-Integrity & Packaging) team is part of Annapurna Labs’ Chip development team. The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.

The team’s work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGA’s substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.

We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years’ experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities

As a SIP engineer, you will be involved in:

• Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
• End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
• Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

Basic qualifications

• BSc in Electrical Engineering or in related field
• 1-3 years of experience in board design, or lab measurement of digital high-speed interfaces or layout or physical design.
• Familiarity with Signal and Power integrity simulation tools.

Preferred qualifications

• Experience with high-speed digital interfaces such as DRAM/PCIe/SerDes.
• Previous experience with lab equipment (e.g oscilloscope, spectrum analyzer)
• Experience with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice)

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