Analog Design, Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years working at the boundary between analog design and customer-facing deliverables, and you know that a model is only as good as the confidence it gives the engineer using it.

You are comfortable moving between SPICE simulations, characterization data, and behavioral model extraction without losing sight of what the customer needs to close timing on their board.

High-speed interfaces like DDR5, LPDDR5, HBM3, and UCIe do not intimidate you. You understand their signaling protocols, their edge cases, and what makes a timing model trustworthy at 6400 MT/s. At Synopsys, you will build the timing and IBIS models that memory controllers and PHY customers depend on to bring up their systems.

What You'll Be Doing

• Generate and validate IBIS models for DDRn, LPDDRn, HBM, and UCIe memory interface IP products, ensuring compliance with industry standards
• Develop timing characterization data and customer-facing timing collateral for board-level design and signal integrity analysis
• Extract behavioral models from transistor-level simulations and correlate them against silicon characterization results across PVT corners
• Work with analog design teams to capture circuit behavior and ensure models reflect real silicon performance
• Debug model discrepancies, timing violations, and signal integrity issues reported by customers or internal validation teams

The Impact You Will Have

• Enable customers to successfully integrate Synopsys memory interface IP into their SoCs with accurate, reliable timing and IBIS models
• Reduce customer support escalations and silicon respins by catching model inaccuracies before tape-out
• Accelerate time-to-market for advanced memory products by streamlining the characterization and model release process
• Improve model quality and consistency across DDR, LPDDR, HBM, and UCIe product families through rigorous validation
• Support signal integrity closure for high-speed memory interfaces operating at multi-gigabit data rates in AI and data center applications

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field
• 5+ years of hands-on experience in analog/mixed-signal design, characterization, or modeling for high-speed interfaces
• Strong understanding of IBIS modeling standards and timing model formats used in memory interface design
• Direct experience with DDR, LPDDR, HBM, or other high-speed memory interface protocols and signaling
• Proficiency with SPICE simulation tools such as HSPICE or Spectre for transistor-level characterization and model extraction
• Experience with scripting languages like Python, Perl, or Tcl for automation is a strong plus

Who You Are

• You can look at a timing violation or an IBIS model mismatch and quickly narrow down whether it is a corner case issue, an extraction problem, or a real circuit behavior
• You communicate model assumptions and limitations clearly to both design teams and customers without burying important details in jargon
• You work well with cross-functional teams including circuit designers, layout engineers, and applications engineers who depend on your models
• You take ownership of your deliverables from initial extraction to final customer release,.

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.