Principal NPU Microarchitect

About Rivian

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Role Summary

We are seeking a Principal Microarchitect to lead the definition of Rivian’s next-generation Neural Network Accelerator Engine (NPU) microarchitecture. This role is aligned to Rivian’s Professional track at RIV-8 (Principal), where the expectation is broad technical expertise, ownership of critical silicon design matters, and work that shapes future vehicle computing platforms.

You will drive the hardware microarchitecture of the compute core with emphasis on execution datapath design, hardware scheduling, quantization-aware execution units, silicon partitioning , and performance scalability for production deep learning workloads. At Rivian, the RAP1 SoC compute engine includes a large processing array ( e.g., systolic arrays or tensor cores ), configurable partitioning, instruction DMA engines, data DMA engines, and substantial on-chip SRAM. This is a deeply cross-functional silicon architecture role spanning compute logic, memory hierarchy/movement, hardware-software co-design , and physical system constraints.

This is a silicon/hardware microarchitecture role focused on ASIC/SoC design for AI compute accelerators. It is not an IT networking, infrastructure, or telecommunications position.

Responsibilities

• Define and evolve the NPU core microarchitecture, including compute datapaths, instruction flow, hardware scheduling strategy, quantization support, and execution efficiency for deep learning inference workloads.
• Architect solutions that map effectively onto Rivian’s custom hardware model, including the processing array, silicon partitioning strategy, and coordination of instruction and data movement across the engine.
• Drive architectural tradeoffs across PPA (Performance, Power, Area), utilization, latency, and scalability.
• Lead the definition of mechanisms for efficient movement of tensor activations, weights, and outputs through on-chip and off-chip memory pathways and high-throughput DMA architecture.
• Partner closely with compiler, model, firmware, RTL design, hardware verification, and SoC teams to ensure ML models are translated into efficient executable flows for the accelerator. Rivian’s compiler flow translates neural network model descriptions into raw instruction streams executed on the hardware, making tight hardware-software co-design essential.
• Define architectural requirements for correctness, observability, resiliency, and debuggability, including support for silicon-level error handling, recovery hooks, and functionally safe execution flows where needed.
• Build cycle-accurate or architectural performance models, evaluate hardware bottlenecks, and guide design decisions with data across representative production workloads.
• Influence long-range accelerator direction, establish technical principles, and serve as a key architecture voice across the silicon organization. At the RIV-8 level, this role is expected to contribute to company objectives and use broad expertise to resolve critical silicon design matters.
• Mentor engineers across architecture and implementation disciplines and raise the technical bar for AI hardware accelerator design at Rivian.

Qualifications

• Deep expertise in computer architecture, logic design, and silicon microarchitecture, with a strong track record of taking complex compute blocks from concept through tape-out and production.

• Strong understanding of machine learning inference hardware components, including custom execution datapath design, hardware-managed scheduling, numerical formats, quantization, and microarchitectural performance optimization.

• Direct experience architecting, modeling, or designing specialized compute engines such as NPUs, TPUs, AI accelerators, vector/SIMD/tensor processors, or systolic arrays.

• Direct experience architecting, modeling, or designing specialized compute engines such as NPUs, TPUs, AI accelerators, vector/SIMD/tensor processors, or systolic arrays.

• Expert knowledge of on-chip memory hierarchy and hardware data movement, including SRAM bank organization, high-throughput DMA engines, multi-buffered structures, bandwidth management, and latency hiding techniques.

• Experience working across the hardware-software boundary, explicitly partnering with compiler teams, runtime development, or ML model deployment teams on hardware-software co-design.

• Proven ability to evaluate architectural tradeoffs using cycle-level, trace-driven, or analytical performance modeling, analysis, and empirical workload characterization.

• Excellent communication skills and the ability to drive technical alignment across RTL design, hardware verification, physical design, firmware, compiler, and product teams.

• Deep expertise in computer architecture and hardware microarchitecture , with a strong track record designing complex silicon blocks from concept through production.

• Strong understanding of neural network inference hardware , including datapath design, scheduling, numerical formats, quantization, and performance optimization.

• Experience architecting or optimizing specialized compute engines such as NPUs , AI accelerators , vector/tensor processors , or systolic-array-based architectures .

• Strong knowledge of memory hierarchy and data movement, including SRAM organization, DMA-based transfer models, buffering, bandwidth management, and latency hiding.

• Experience working across hardware and software boundaries, especially with compiler , runtime , or model deployment teams.

• Proven ability to evaluate architectural tradeoffs using modeling, analysis, and empirical workload characterization.

• Excellent communication skills and the ability to influence across architecture, design, verification, physical design, firmware, compiler, and product teams.

• BS, MS, or PhD in Electrical Engineering , Computer Engineering , or a related field.

Preferred Qualifications

• Experience with automotive SoC or safety-critical silicon development (e.g., ISO 26262, ASIL requirements).

• Experience mapping production deep learning workloads—such as Transformers, CNNs, or Large Language Models (LLMs)—onto custom hardware fabrics, particularly in perception and autonomy contexts.

• Familiarity with instruction-driven accelerator architectures, partitioned compute fabrics, and high-efficiency memory orchestration.

• Hands-on experience with hardware modeling frameworks (e.g., SystemC, C++, Python architectural simulators) or pre-silicon emulation.

• Experience defining architecture for systems that must strictly balance throughput, determinism, power efficiency, and silicon-level debuggability.

Pay Disclosure

The listed base salary range for this role is $218,000 - $312,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

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