Applications Engineering, Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring foundational knowledge of signoff and understand how extraction or verification errors can affect schedules and costs. You are interested in translating technical results into clear, actionable guidance for design teams and have academic, internship, or early-career exposure to parasitic modeling, timing correlation, or design rule compliance. You can communicate technical findings clearly and are motivated to expand your expertise through hands-on customer engagements.

You excel at debugging complex technical issues, including multi-corner extraction problems that appear only at specific process nodes, difficult-to-explain RC modeling anomalies, and physical signoff issues involving design rule checking, layout-versus-schematic verification, and full-chip analysis. You take a systematic, evidence-based approach and investigate each issue until the root cause is identified. Your customer experience enables you to understand the need behind each request and guide discussions toward practical solutions. At Synopsys, you will help design teams address some of the industry's most complex extraction and physical signoff challenges.

What You'll Be Doing

• Provide direct technical support to design teams using ICV and StarRC to improve signoff readiness and support successful tape-outs
• Debug complex ICV physical verification and StarRC parasitic extraction issues, including design rule violations, layout-versus-schematic discrepancies, RC modeling anomalies, and timing correlation problems across advanced process nodes
• Develop and refine ICV and StarRC signoff methodologies that improve verification and extraction accuracy, reduce runtime, and support reliable full-chip analysis at scale
• Collaborate with customer engineering teams and senior colleagues during critical tape-out phases to analyze blocking ICV and StarRC issues and contribute to solutions that support full-chip scalability
• Assist with technical guidance and training for customer teams on ICV and StarRC workflows, physical verification, RC modeling techniques, and signoff best practices, while documenting and sharing key learnings with the broader field organization
• Work directly with Synopsys R&D teams to communicate customer requirements, reproduce ICV and StarRC issues, and validate fixes and enhancements
• Document technical solutions, methodology improvements, and common ICV and StarRC failure modes to build reusable knowledge for the broader applications engineering team
• Leverage AI-driven techniques to help customers develop and optimize design methodologies, accelerate issue analysis, and improve engineering productivity across ICV and StarRC workflows

The Impact You Will Have

• Enable customers to achieve faster, more reliable signoff closure on cutting-edge semiconductor designs
• Reduce extraction and timing correlation issues that would otherwise delay tape-outs or cause silicon respins
• Help customers scale signoff workflows to handle increasingly complex, multi-billion-transistor designs
• Accelerate problem resolution across team by creating reusable debugging frameworks and documented solutions
• Improve ICV and StarRC adoption and effectiveness across customer design teams through hands-on methodology development
• Build trust and technical credibility with demanding semiconductor customers, strengthening long-term relationships with Synopsys
• Influence product roadmap priorities by surfacing real customer pain points and use cases to R&D

What You'll Need

• Entry-level to approximately 2 years of relevant experience in applications engineering, semiconductor design, physical verification, or parasitic extraction; strong new graduates are also encouraged to apply
• Foundational knowledge of physical verification and parasitic extraction, with experience using EDA tools; hands-on exposure to ICV and/or StarRC is preferred
• Basic understanding of semiconductor design, foundry flows, design rule checking, layout-versus-schematic verification, and RC extraction concepts
• Working knowledge of Linux/Unix environments and scripting languages such as Tcl or Python
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field; no specific certification is required
• Strong problem-solving, communication, customer engagement, teamwork, and learning agility, with the motivation to develop into a trusted Field Application Engineer
• Strong Korean and English communication skills are preferred for customer engagement and collaboration with global Business Unit and R&D teams

Who You Are

• You approach technical issues with curiosity and a structured problem-solving mindset, asking focused questions to identify the most effective starting point
• You can work with incomplete information, separate relevant signals from noise, and make steady progress through evidence-based analysis
• You communicate technical concepts clearly and concisely, adapting the level of detail to the audience without losing accuracy
• You are comfortable acknowledging what you do not yet know, develop a clear plan to find the answer, and learn quickly from each experience
• You engage customers and colleagues with professionalism, listen carefully to their needs, and offer constructive technical guidance when expectations need to be aligned
• You take ownership of assigned issues, follow through on commitments, and understand the importance of timely, high-quality support to customers

The Team You'll Be Part Of

You will join the Global Signoff Organization that supports customers using ICV and StarRC across physical verification and parasitic extraction workflows. You will collaborate closely with customer engineering teams and with global Business Unit and R&D organizations to analyze technical issues, improve design methodologies, and deliver effective signoff solutions. The team provides hands-on guidance, mentoring, and opportunities to build both technical expertise and customer-facing skills as you grow in the Field Application Engineer role.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.