Executive Director SOC Physical Design

Executive Director, SoC Physical Design

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars and artificial intelligence to cloud computing, 5G, high-performance computing, and the Internet of Things. We lead in chip design, verification, and IP integration, enabling customers to create advanced, high-performance silicon.

The Systems Solutions Group (SSG) delivers architecture, design creation, verification, physical implementation, tools, methodologies, and IP expertise to help leading customers complete their most challenging SoC projects. Our work spans complex IP and subsystems through full turnkey, end-to-end SoCs across markets including high-performance computing, consumer, automotive, aerospace and defense, and AI.

Within our HPC controller portfolio, rapidly evolving standards and increasing I/O speeds demand new architectures and increasingly sophisticated physical implementation strategies. Physical design feasibility must be an integral part of product development and production-quality sign-off to ensure our soft IP can be successfully mapped to advanced ASIC technologies and delivers an exceptional customer experience.

The Role

We are seeking an Executive Director, SoC Physical Design to provide strategic, technical, and organizational leadership for physical design and implementation across complex SoCs, subsystems, and HPC controller IP. This is a hands-on executive leadership role combining deep physical design expertise with team leadership, customer engagement, program execution, methodology development, and cross-functional influence.

You will build, grow, and lead a multi-site physical design organization and be accountable for physical feasibility, implementation readiness, and design closure across a broad configuration space. You will partner closely with architects, RTL designers, verification teams, methodology and EDA teams, business-unit application engineers, Sales, and customers to translate requirements into executable plans and high-quality silicon-ready solutions.

You will also drive continuous improvements in design architecture, constraints, flows, tools, and methodology to improve power, performance, area, turnaround time, and overall implementation quality.

What You’ll Be Doing

• Build, grow, manage, and lead a cohesive, high-performing physical design organization across multiple sites and customer engagements.
• Own physical design strategy, planning, execution, and sign-off for complex SoCs, subsystems, IP, and HPC controller products.
• Be accountable for physical feasibility and implementation readiness of soft IP releases, with practical P&R validation across representative configurations and technology targets.
• Lead end-to-end physical implementation, including floor planning, hierarchical design, placement, clock tree synthesis, routing, timing closure, power optimization, physical verification, and tape-out readiness.
• Establish scalable physical design flows, methodology, quality standards, and sign-off criteria across the product configuration space.
• Drive timing closure, power optimization, congestion resolution, constraint quality, and implementation efficiency using Synopsys tool flows such as Fusion Compiler.
• Partner with architecture and RTL design teams to identify structural and design improvements required for physical success, providing clear and actionable technical direction.
• Collaborate with verification, pre-silicon, post-silicon, and emulation teams to ensure implementation requirements and design tradeoffs are addressed throughout the development lifecycle.
• Work directly with customers to understand requirements, define scope, assess feasibility, estimate effort, cost, schedule, and design complexity, and support implementation on their selected technology nodes.
• Support customers with floorplan development, P&R execution, design closure, and adoption of Synopsys tools, methodologies, and IP.
• Develop and maintain consistent physical implementation user guides for each product vertical, including constraints, recommended flows, methodology, and sign-off guidance.
• Interface with methodology, EDA tooling, application engineering, and product teams to drive improvements in tools, flows, automation, and engineering productivity.
• Review implementation results, reports, metrics, and deliverables; provide continuous feedback and corrective direction to improve quality and execution.
• Report program status, risks, dependencies, and recommendations to senior leadership, proactively resolving issues that could affect delivery.
• Mentor technical leaders and engineers, strengthen organizational capabilities, and establish a culture of technical excellence, accountability, collaboration, and continuous improvement.
• Partner with other Synopsys teams, including business-unit AEs and Sales, to broaden and deploy differentiated tool and IP solutions for customers.
• Ensure adherence to engineering quality standards, processes, and best practices across the organization.

The Impact You Will Have

• Ensure complex SoC and soft IP releases are physically feasible, implementation-ready, and capable of meeting demanding power, performance, area, quality, and schedule targets.
• Improve design readiness and physical implementation success across advanced ASIC technology nodes.
• Increase the quality and consistency of delivered constraints, implementation guidance, and sign-off criteria.
• Improve customer experience and success in floor planning, P&R, and design closure of Synopsys IP and SoC solutions.
• Drive architecture and RTL improvements based on real implementation data and physical design insight.
• Increase engineering productivity through scalable flows, automation, methodology, and stronger collaboration across design and implementation teams.
• Build a strong culture of ownership, teamwork, technical rigor, and predictable execution.
• Provide actionable technical and program insights that enable effective executive decision-making.

What You’ll Need

• BS/MS in Electronics, Electrical Engineering, or a related discipline, with extensive experience in ASIC/SoC development and physical design; approximately 20+ years of relevant semiconductor experience is preferred for this executive-level role.
• Deep expertise in physical design with a proven track record of hardening complex designs through tape-out readiness.
• Extensive hands-on knowledge of floor planning, placement, clock tree synthesis, routing, static timing analysis and timing closure, power optimization, hierarchical implementation, constraints, and physical sign-off.
• Strong experience with Synopsys physical implementation tool flows, including Fusion Compiler, or equivalent advanced-node implementation platforms.
• Strong understanding of ASIC development flows, SoC architecture, RTL design considerations, verification dependencies, and the stakeholders involved in successful silicon delivery.
• Demonstrated ability to evaluate physical feasibility and guide architecture and RTL teams toward implementation-friendly designs.
• Experience developing scalable flows, sign-off methodology, production-quality checks, and physical implementation guidance across multiple product configurations and technology nodes.
• Proven experience leading large, geographically distributed engineering teams and developing senior technical talent.
• Strong program and operational management experience, including planning, resource management, schedule ownership, risk management, and delivery across multiple concurrent programs.
• Experience working directly with customers on complex implementation challenges and supporting deployment across customer-selected technology nodes.

…